1. Technical Field
This disclosure relates to memories, and more particularly to shared memory I/O.
2. Description of the Related Art
Many memory devices include a number of storage arrays that share an input/output I/O circuit. For example, two or more arrays may share an I/O circuit that includes a sense amplifier. These storage arrays may often operate in voltage domains that are different from one another and which are also different than the voltage domain of the shared I/O. In many cases, the storage arrays and their associated circuits may be placed in retention mode or powered down altogether to save power. However, when an array is powered down or placed in retention there is no input to the sense amplifiers and the data output signal paths must be clamped to an appropriate valid signal level.
The clamping is typically done using a clamping stage after the output of an I/O latch circuit. Clamping stages may in some cases cause additional signal delay because they are in the signal path, and thus the critical path. Furthermore, the additional clamping stage may consume die area.